Decoder structure and method for FPGA configuration

Details Decoder structure and method for FPGA configuration Decoder structure and method for FPGA configuration

1997-12-30

2000-02-22

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 39, 326 40, 326 41, 395651, G06F 738, H03K 19173

Patent

active

060284455

ABSTRACT:
A method is provided for configuring an FPGA using a decoder implemented in the FPGA. Specifically, an external configuration device or an embedded non-volatile memory configures a first portion of the FPGA as a decoder. Encoded configuration data is transferred to the decoder, which then configures other portions of the FPGA. In one embodiment, the decoder is a decompression unit, which decompresses compressed configuration data. In another embodiment, the decoder is an interpreter, which interprets configuration commands. In some embodiments, the portion of the FPGA used for the decoder can be reconfigured after the configuration of the other portions of the FPGA.

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