Method of planarizing a pre-metal dielectric layer using chemica

Details Method of planarizing a pre-metal dielectric layer using chemica Method of planarizing a pre-metal dielectric layer using chemica

1997-06-30

2000-02-22

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438631, 438633, H01L 214763

Patent

active

060279966

ABSTRACT:
A method of planarizing a pre-metal dielectric layer using chemical-mechanical polishing, in order to alleviate the problem of resistance reduction when making products having poly-loads, includes providing a semiconductor substrate with a semiconductor component formed thereabove. A pre-metal dielectric layer is formed above the semiconductor substrate. Thereafter, the pre-metal dielectric layer is planarized using chemical-mechanical polishing. Next, a silicon-rich oxide layer, that has a characteristic gettering property which can be used to compensate for the weakening of the gettering ability of the pre-metal dielectric layer, due to the wearing out of the layer in a chemical-mechanical polishing operation, is formed above the pre-metal dielectric layer.

REFERENCES:
patent: 5290727 (1994-03-01), Jain et al.
patent: 5382545 (1995-01-01), Hong
patent: 5403780 (1995-04-01), Jain et al.
patent: 5763937 (1998-06-01), Jain et al.

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