Method for forming a DRAM cell with a fork-shaped capacitor

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

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438253, H01L 218242

Patent

active

060279818

ABSTRACT:
A method for forming a fork-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first doped polysilicon layer (118) over a semiconductor substrate (110), wherein at least a portion of the first doped polysilicon layer communicates to the substrate. A first dielectric layer (119) is formed on the first doped polysiliocn layer, and is then patterned to define a storage node therein. Next, a second doped polysilicon layer (122) is formed on the first dielectric layer and the first doped polysilicon layer, and a second dielectric spacer (124) is formed on a sidewall of the second doped polysilicon layer. After etching the second doped polysilicon layer and the first doped polysilicon layer using the second dielectric spacer as a mask to expose surface of the first dielectric layer, a third doped polysiliocn spacer (126) is formed on a sidewall of the second dielectric spacer. The second dielectric spacer and the first dielectric layer are then removed, and a fourth dielectric layer (136) is formed on the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysiliocn spacer. Finally, a conductive layer (138) is formed on the fourth dielectric layer.

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