Chip select speedup circuit for a memory

Details Chip select speedup circuit for a memory Chip select speedup circuit for a memory

1992-10-28

1994-04-05

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36523006, G11C 700

Patent

active

053011651

ABSTRACT:
A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to select mode, there appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such a false transition as an actual transition, local clock pulse generators are used which only detect high to low transitions in the chip select mode.

REFERENCES:
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patent: 4970694 (1990-11-01), Tanaka et al.
patent: 5025422 (1991-06-01), Moriwaki
Technical Disclosure Bulletin, vol. 31, No. 5, Oct. 1988, pp. 335-336.

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