Static information storage and retrieval – Read/write circuit – Testing
Patent
1991-07-18
1994-04-05
Pascal, Robert J.
Static information storage and retrieval
Read/write circuit
Testing
371 223, 371 224, 371 225, G11C 700
Patent
active
053011562
ABSTRACT:
A configurable self-test circuit for a RAM embedded in an integrated circuit chip comprises an incrementable address register, a configurable control circuit, a write register, a signature generator, and a scanpath. The address register stores the current RAM address to be accessed and is adapted to automatically increment the RAM address by an address increment upon receiving an increment signal. The configurable control circuit has a normal operation mode and three test modes wherein all writes, all reads or alternating writes and reads are performed. The write register stores data patterns which are to be written to the RAM under test. The signature generator receives data read from the RAM and produces a unique signature in response thereto. A scanpath through the address register, control circuit, write register, and signature generator allows test vectors to be serially shifted in and test data to be shifted out of these devices. A full functional test is performed of the RAM. A special test checks the functioning of the pull-up FETs in each RAM cell.
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Dekker, R., et al. "Realistic Built-in Self-test for Static RAMs," IEEE Design & Test of Computers, Feb. 1989, pp. 26-354, (IEEE Order No. 0740-7475/89/002-26$1.00).
Hassan, S., et al., "Parallel Signature Analyzers-Detection Capability and Extensions," Apr. 1983, (IEEE order number 4/83/0000-0440$1.00).
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Dekker, R., et al. "Fault Modeling and Test Algorighm Development for Static Random Access Memories," Proc. IEEE Int'l Test Conf., Sep. 1988, pp. 343-352 (IEEE Order No. CH2610-45/88/0000/0343$01.00).
Dinh Tan
Hewlett--Packard Company
Kelley Guy J.
Pascal Robert J.
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