Synchronous semiconductor memory device having wave pipelining c

Details Synchronous semiconductor memory device having wave pipelining c Synchronous semiconductor memory device having wave pipelining c

1998-10-27

1999-12-21

Le, Vu A.

Static information storage and retrieval

Addressing

Sync/clocking

3652335, 365194, G11C 700

Patent

active

060058250

ABSTRACT:
A synchronous semiconductor memory device having a wave pipelining control structure and a method of outputting data therefrom. A register for storing the data output from a memory cell is controlled by a control signal in response to first and second external clock signals. The level transition of the control signal derived from the first clock is delayed, so that data output malfunctioning is prevented even though manufacturing process conditions are changed.

REFERENCES:
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5581512 (1996-12-01), Kitamura
patent: 5822254 (1998-10-01), Koshikawa et al.
1996 Symposium on VISI Circuits Digest of Technical Paper, pp. 192-193, "Skew Minimization Techniques for 256M-bit Synchronous DRAM and Beyond" Jin-Man Han, et al.
1995 ISSCC Digest of Technical Papaers, pp. 250-251, by Hoi-Jun Yoo, et al.
IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1665, by Takanori Saeki, et al.

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