Semiconductor memory device with column redundancy

Details Semiconductor memory device with column redundancy Semiconductor memory device with column redundancy

1991-11-07

1992-12-01

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Bad bit

36512905, 36523006, 371 103, G11C 2900

Patent

active

051684683

ABSTRACT:
A semiconductor memory device comprises a memory cell array, a redundant memory cell array, bit line pairs, spare bit line pairs, a column address information storage circuit having stored therein information of a column address of a faulty cell and a column address of a spare cell, column decoders, a first column selecting gate for connecting one of the bit line pairs and first data output line pairs, a second column selecting gate for connecting one of the bit line pairs and a second data output line pair, a spare column decoder for selecting a third or a fourth column selecting line, a third column selecting gate for connecting the spare bit line pairs and the first data output line pairs, a fourth column selecting gate for connecting the spare bit line pairs and the second data output line pair, a first buffer for selecting two data and amplifying and outputting, a second buffer for amplifying and outputting data from the second data output line pair, and a register for storing therein data from the first and/or second buffers.

REFERENCES:
patent: 5058069 (1991-10-01), Gaultier et al.

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