Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

1991-01-16

1992-12-01

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257637, 257640, 257648, H01L 2968, H01L 2978, H01L 2934

Patent

active

051683342

ABSTRACT:
A small-area single-transistor EEPROM memory cell includes buried bit lines (44,46) extending through the array and connecting together many memory cells. Formed above a channel area (25) and between the bit lines (44,46) are oxide-nitride-oxide layers (50,52,54) for providing isolation between overlying polysilicon word lines (56, 66) and the underlying conduction channel (25). The nitride layer (52) provides the charge retention mechanism for programming the memory cell. The word lines (56, 66) provide electrical contact to a number of memory cells in the row. Electrical contact is made to the word lines (56, 66) by metal contacts (68, 70), and to the bit lines (44,46) by metal contacts (72, 74) at the array periphery, thereby avoiding metal contacts to every memory cell of the array. A EEPROM memory cell of 4-5.2 microns can be fabricated.

REFERENCES:
patent: 4360900 (1982-11-01), Bate
patent: 4373248 (1983-02-01), McElroy
patent: 4377818 (1983-03-01), Kuo et al.
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4768080 (1988-08-01), Sato
patent: 4774556 (1988-09-01), Fujii et al.
A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device, T. Y. Chan, K. K. Young, and Chenming Hu, IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987.

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