Transistor gate formation

Details Transistor gate formation Transistor gate formation

1993-10-13

1995-07-11

Dang, Thi

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437228, H01L 2100

Patent

active

054317703

ABSTRACT:
A method for forming transistors having sublithographic features, for example, gates, is disclosed. A patterned hardmask (formed, for example from PETEOS) is created overlying oxide and polysilicon layers. The dimensions of the hardmask are reduced by isotropic etching. The reduced-dimension hardmask is used with an anisotropic etching process to define a reduced-dimension feature such as a gate.

REFERENCES:
patent: 4460435 (1984-07-01), Maa
patent: 5139904 (1992-08-01), Auda et al.
patent: 5169487 (1992-12-01), Langley et al.

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