Image analysis – Histogram processing – For setting a threshold
Patent
1989-05-19
1991-12-24
Atkinson, Charles E.
Image analysis
Histogram processing
For setting a threshold
371 681, G01R 3128
Patent
active
050758926
ABSTRACT:
A parallel read circuit for testing high density memories is disclosed which reduces testing time by increasing the simultaneous testing data imputted. Individual data line sense amplifiers are arrayed in parallel with corresponding multiplexers to amplify respective data bits from respective output data lines for each of the plural cell array blocks; data line comparators are connected at a position downstream of the individual data line sense amplifiers to compare the amplified data from said sense amplifiers per each separate cell array block and form primarily compared data, these primarily compared data are sent to the pertinent one of the data buses and individual output buffers are connected at a position downstream of the data buses to buffer further the test output from the data line comparators during a test mode in order to locate the specific location of defective memory block.
REFERENCES:
patent: 4055754 (1977-10-01), Chesley
patent: 4541090 (1985-09-01), Shiragasawa
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4768194 (1988-08-01), Fuchs
patent: 4833677 (1989-05-01), Jarwala et al.
patent: 4885748 (1989-12-01), Hoffmann et al.
Atkinson Charles E.
Samsung Electronics Co,. Ltd.
LandOfFree
Parallel read circuit for testing high density memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel read circuit for testing high density memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel read circuit for testing high density memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-49939