Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1989-06-02

1990-06-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365208, 365210, G11C 700

Patent

active

049319965

ABSTRACT:
A semiconductor memory device for reading stored data from a selected memory cell in the semiconductor device to a sensing amplifier. An array of memory cells is arranged in a matrix, each memory cell including a MOS transistor. Word lines are organized to select groups of the MOS transistors. A plurality of first bit lines are arrayed in a matrix with the word lines. The word lines and bit lines together select the selected memory cell from the array. Each first bit line is coupled to either the source electrode or drain electrode of a plurality of MOS transistors. There is at least one second bit line. Each second bit line is selectively coupled to at least two corresponding first bit lines. A first bit line selection circuit selectively couples one of the first bit lines to a corresponding second bit line. A first power source line is coupled to the other of the source and drain of the array of the MOS transistors. A second bit line select means selectively couples a second bit line to the sensing amplifier.

REFERENCES:
patent: 4301518 (1981-11-01), Klaas
"An 80 ns 1 Mb ROM" by Fujio Masuoka, et al., 1984, IEEE International Solid-State Circuits Conference, pp. 146, 147 and 329.
"4M Bit Mask ROM And The Application Therefore", by Shoichi Tsujita, Electronic Parts and Materials, published 1/1/86, pp. 104-108.

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