Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Patent
1980-06-02
1983-08-02
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
365203, 365208, G11C 700, G11C 706
Patent
active
043970036
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to semiconductor integrated circuits and in particular to a random access memory which utilizes dynamic memory cells.
BACKGROUND ART
The operation of previous dynamic random access memory circuits is described in U.S. Pat. No. 3,588,844 and 3,514,765 to Christeneon, U.S. Pat. No. 3,699,537 to Wahlstrom and U.S. Pat. No. 3,902,082 and 3,969,706 to Proebsting et al. As shown in the Wahlstrom and Proebsting Patents, it has been the practice to use sense amplifiers to detect voltage differentials on bit lines which have had memory cells connected thereto. The connection of the memory cell to the bit line changes the previously established voltage on the bit line to estabish the desired data state as a voltage differential on the bit lines. However, the voltage change on a bit line caused by the connection of a memory cell thereto is very small and the detection of such a small voltage change has presented a serious problem in the design of dynamic random access memories. A further problem is that electrical noise can be picked up by the bit lines and this noise can mask the desired voltage offset produced by a memory cell. Further, integrated circuit fabrication tolerances can result in unbalanced bit lines which also interfere with the reading of a memory cell.
In response to these problems, it has heretofore been the practice to incorporate a dummy cell with each bit line of the memory. The dummy cells are precharged to a given voltage state and are connected during each memory cycle to the nonselected bit line within each pair of bit lines. However, the inclusion of a large number of dummy cells together with their associated circuitry increases the size of the integrated circuit and adds to the circuit complexity.
In view of the above problems, there exists a need for a dynamic random access memory which operates in such a method so as not to require a dummy cell for each bit line while at the same time providing reliable identification of the voltage states stored in the memory cells.
DISCLOSURE OF THE INVENTION
The present invention provides a method for operating a dynamic random access memory in the following steps. A high or low voltage state is stored in a dynamic memory cell where the high voltage state corresponds to a first data state and the low voltage state corresponds to a second data state. The memory cell is then connected to one of a pair of bit lines after the bit lines have been set to an intermediate voltage state. When a memory cell storing a low voltage is connected to the bit line, the voltage on the bit line is decreased. When a memory cell storing a high voltage is connected to the bit line, the voltage on the bit line is increased. When the voltage state on one bit line is being changed by the connection of a memory cell thereto, the complementary bit line of the pair of bit lines is maintained essentially at the intermediate voltage state which had been set thereon. After the memory cell has been connected to one of the bit lines, the bit line having the lowest voltage thereon is driven to a low voltage state, and the other of the bit lines is driven to a high voltage state. The memory cell is disconnected from the corresponding bit line after the corresponding bit line has been driven to either the low voltage state or the high voltage state. After the memory cell has been disconnected from the corresponding bit line, the bits lines are connected together to equilibrate the voltages on the bit lines to establish the intermediate voltage state in preparation for a new cycle.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic illustration of the dynamic random access memory in accordance with the present invention; and
FIG. 2 is a set of timing diagrams illustrating the various signals which occur in the dynamic random acces
REFERENCES:
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4061999 (1977-12-01), Proebsting et al.
patent: 4290120 (1981-09-01), Stein
patent: 4291393 (1981-09-01), Wilson
Foss, Richard C., and Harland, Robert, "Simplified Peripheral Circuits for a Marginally Testable 4k RAM", IEEE International Solid-State Circuits Conference, Feb. 1975, pp. 102-103.
Foss, Richard C., "The Design of MOS Dynamic RAMs", IEEE International Solid-State Circuits Conference, Feb. 1979, pp. 140-141.
Proebsting Robert J.
Wilson Dennis R.
Hecker Stuart N.
Mostek Corporation
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