Process for producing an integrated circuit including a J-FET an

Details Process for producing an integrated circuit including a J-FET an Process for producing an integrated circuit including a J-FET an

1976-08-09

1977-07-12

Van Horn, Charles E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29591, 148 15, 148188, 156643, 156649, 357 22, 357 91, 427 91, H01L 21225, H01L 21265

Patent

active

040352072

ABSTRACT:
A process for producing an integrated circuit having a pair of complementary field effect transistors, one being a J-FET and the other being a MIS-FET. The process includes a series of masking and ion implantation steps carried out in part for both transistors at the same time. The doping of the region between the source and drain is increased for the MIS-FET at the same time that the doping of the channel of the J-FET is increased in order to control the threshold voltage of the MIS-FET.

REFERENCES:
patent: 3793088 (1974-12-01), Eckton
patent: 3806371 (1974-04-01), Baron
patent: 3898105 (1975-08-01), Mai et al.
patent: 3920484 (1975-11-01), Ogura et al.
patent: 3969744 (1976-07-01), Nicholas et al.
patent: 3986896 (1976-10-01), Ueno et al.

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