Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1998-03-20
2000-10-17
Cabeca, John W.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
709301, 711170, 711173, 711203, G06F 1202
Patent
active
061346411
ABSTRACT:
A method of and a system for allowing cacheable system memory to be accessed in a non-cacheable manner. In one embodiment of the present invention, a computer system is tricked during POST (Power-On Self-Test) to reserve a first region in a non-cacheable address space for a virtual peripheral device. The computer system is then tricked during operating system startup to reserve a second region in a cacheable address space. In the present embodiment, the first region is then mapped to the second region such that accesses to the first region is automatically forwarded to the second region. As a result, objectives of the present invention are achieved as cacheable memory may be accessed via accessing non-cacheable memory of the computer system.
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"Accelerated Graphics Port Interface Specification";Intel Corporation;1996.
Cabeca John W.
Chace Christian P.
VSLI Technology, Inc.
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