Planarization of metal films for multilevel interconnects

Electric heating – Metal heating – By arc

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2191218, 437 19, B23K 2600

Patent

active

048145785

ABSTRACT:
In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

REFERENCES:
patent: 4549064 (1985-10-01), Delfono

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