Integrated circuit with planarized dielectric layer between succ

Details Integrated circuit with planarized dielectric layer between succ Integrated circuit with planarized dielectric layer between succ

1995-10-19

1999-08-24

Reichard, Dean A.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438620, 438488, H01L 2144

Patent

active

059435984

ABSTRACT:
A method of forming a portion of a semiconductor integrated circuit having a semiconductor substrate as well as the resulting integrated circuit. In the inventive method, various steps are involved. In one embodiment, for example, the method steps are as follows. First, there is formed a first polysilicon layer overlying and in contact with the semiconductor substrate. Second, a plurality of conductive structures are patterned from the first polysilicon layer. Third, there is formed a dielectric layer having an upper planar surface and having a lower surface contacting the semiconductor substrate and the plurality of conductive structures from the first polysilicon layer. Fourth, there is formed a second polysilicon layer overlying and in contact with the dielectric layer. Fifth, a plurality of conductive structures are formed from the second polysilicon layer. Lastly, there is formed a metallic layer over the plurality of conductive structures from the second polysilicon layer.

REFERENCES:
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patent: 5494859 (1996-02-01), Kapoor
patent: 5524339 (1996-06-01), Gorowitz et al.
patent: 5578796 (1996-11-01), Bhatt et al.
patent: 5684312 (1997-11-01), Yonemoto
"Techniques for Planarizing Device Topolography," Kathy Sidmore, Associate Editor, Apr. 1988 Semiconductor International, pp. 5, 115-119.
"Silicon Processing for the VLSI Era, vol. 1: Process Technology,"Stanley wolf and Richard N. Tauber, Chapter 6: Chemical Vapor Deposition of Amorphous and Polycrystalline Thin Filmes, pp. 161, 182-197, Lattice Press, SunsetBeach, California, 1986.

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