Parallel access memory system

Details Parallel access memory system Parallel access memory system

1976-11-29

1978-05-30

Konick, Bernard

Boots, shoes, and leggings

365219, 340324AD, G06F 300, G06F 1300

Patent

active

040927288

ABSTRACT:
Memory system having contiguous storage locations with sequential addresses is partitioned into units to permit separate unit write-in and parallel unit read-out, operations. Each unit is responsive to common word address signals and unique combinations of block address signals. In response to a control signal in a first of two possible states, the memory system operates in a conventional manner, i.e., data is read from or written to a particular location in the memory to or from a data bus, the address of the particular location being supplied over an address bus and having a block select portion and a word select portion. When the control signal is in its second state, each unit is responsive only to the word address signals to read data from or write data to common word locations in each unit simultaneously. Several utilization devices can be similarly arranged so that when the control signal is in the second state, each device is coupled directly to an associated one of the units and all units and devices are decoupled from the data bus. Another embodiment of the invention provides parallel memory access without switching elements. A system is also described which is especially adaptable to color television display of information.

REFERENCES:
patent: 3210733 (1965-10-01), Terzian et al.
patent: 3855580 (1974-12-01), Lighthall et al.
patent: 3858187 (1974-12-01), Lighthall et al.
patent: 4016544 (1977-04-01), Morita et al.

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