Two-transistor DRAM cell for logic process technology

Details Two-transistor DRAM cell for logic process technology Two-transistor DRAM cell for logic process technology

1997-11-26

1999-08-24

Nelms, David

Static information storage and retrieval

Read/write circuit

36518904, 365104, G11C 1604

Patent

active

059432705

ABSTRACT:
A DRAM cell is provided which includes a read bit line capable of being precharged to a first voltage level, a write bit line capable of carrying data, a read word line capable of being asserted at a second voltage level, and a write word line capable of being asserted at about the first voltage level. A first switching device having an enable input is coupled between the read bit line and the word read line. A second switching device having an enable input coupled to the write word line is coupled between the write bit line and the enable input of the first switching device.

REFERENCES:
patent: 5112986 (1992-05-01), Lim
patent: 5262988 (1993-11-01), Ochii

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