Non-volatile memory device and method for operating and fabricat

Static information storage and retrieval – Floating gate – Particular connection

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Details

36518518, 36518524, 36518528, 36518533, G11C 1604

Patent

active

059432624

ABSTRACT:
A non-volatile memory device includes a plurality of bit lines arranged in parallel at predetermined intervals, a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals, a plurality of unit cells having a stacked gate structure comprising a floating gate and a control gate formed in regions where the bit lines and word lines perpendicularly intersect, a plurality of source lines parallel to the bit lines for connecting source active regions of cells to one another, the source active regions being shared by two symmetrical cells connected to an identical bit line through different bit line contacts, and source select transistors formed in overlap regions between source lines and word lines, for dividing the source active regions. For programming a cell, a cell current is generated by applying a positive voltage to a bit line and a word line of the selected cell and a reference voltage lower than the bit line voltage to a source line, and a voltage lower than the reference voltage is applied to a word line of an unselected cell sharing the source active region with the selected cell. Therefore, the limitations of overerasure can be avoided in a device which occupies the same cell area as that of conventional cell arrays.

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