Semiconductor memory device with efficient layout

Static information storage and retrieval – Interconnection arrangements

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365 51, G11C 506

Patent

active

059432535

ABSTRACT:
A semiconductor memory device includes at least one cell block including an array of memory cells, a plurality of sense amplifiers which temporarily hold data of the memory cells, a first data bus connected to the plurality of sense amplifiers via first gates, and a second data bus having a direct electrical connection to the first data bus and being laid out to extend through a position of the at least one cell block.

REFERENCES:
patent: 5499215 (1996-03-01), Halta
patent: 5546349 (1996-08-01), Watanabe et al.
patent: 5657265 (1997-08-01), Yoo et al.
patent: 5838604 (1998-11-01), Tsuboi et al.

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