System for implementing multiple lock indicators on synchronous

Details System for implementing multiple lock indicators on synchronous System for implementing multiple lock indicators on synchronous

1987-05-01

1990-08-14

Williams, Jr., Archie E.

Boots, shoes, and leggings

3642292, 3642468, 3642443, 3642401, 3642426, 36424292, 3642409, 364270, 3642701, 364271, 3642712, 3642716, G06F 1314, G06F 13364, G06F 1342, G06F 1516

Patent

active

049492390

ABSTRACT:
A memory node in a computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to the memory node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.

REFERENCES:
patent: 3398405 (1968-08-01), Carlson et al.
patent: 3528061 (1970-09-01), Zurcher, Jr.
patent: 3761883 (1973-09-01), Alvarez et al.
patent: 3916384 (1975-10-01), Fleming et al.
patent: 3993981 (1976-11-01), Cassarino et al.
patent: 3997875 (1976-12-01), Broeren
patent: 4000485 (1976-12-01), Barlow et al.
patent: 4050059 (1977-09-01), Williams et al.
patent: 4055851 (1977-10-01), Jenkins et al.
patent: 4075692 (1978-02-01), Sorenson et al.
patent: 4099243 (1978-07-01), Palumbo
patent: 4161778 (1979-07-01), Getson, Jr.
patent: 4214304 (1980-07-01), Shimizu et al.
patent: 4296466 (1981-10-01), Guyer et al.
patent: 4313161 (1982-01-01), Hardin et al.
patent: 4315310 (1982-02-01), Bayliss et al.
patent: 4384322 (1983-05-01), Bruce et al.
patent: 4407016 (1983-09-01), Bayliss et al.
patent: 4480307 (1984-10-01), Budde et al.
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4574350 (1986-03-01), Starr
patent: 4587609 (1986-05-01), Boudreau et al.
patent: 4604694 (1986-08-01), Hough
patent: 4621318 (1986-11-01), Maeda
patent: 4626843 (1986-12-01), Szeto et al.
patent: 4660169 (1987-04-01), Norgren et al.
patent: 4665484 (1987-05-01), Nanba
patent: 4698753 (1987-10-01), Hubbins et al.
patent: 4706190 (1987-11-01), Bomba et al.
patent: 4709326 (1987-11-01), Robinson
patent: 4763249 (1988-08-01), Bomba et al.

Affiliated with

Also associated with

Rating

System for implementing multiple lock indicators on synchronous does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for implementing multiple lock indicators on synchronous , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for implementing multiple lock indicators on synchronous will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-467168