Double level polysilicon series transistor cell

Details Double level polysilicon series transistor cell Double level polysilicon series transistor cell

1978-05-18

1980-07-15

Wojciechowicz, Edward J.

357 23, 357 45, 357 41, 357 59, H01L 2702

Patent

active

042131391

ABSTRACT:
A pair of MOS transistors are formed as an integrated semiconductor device, sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask.

REFERENCES:
patent: 4084108 (1978-04-01), Fujimoto
patent: 4099196 (1978-04-01), Simko

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