Semiconductor integrated circuit with dummy pedestals

Details Semiconductor integrated circuit with dummy pedestals Semiconductor integrated circuit with dummy pedestals

1988-06-03

1990-08-14

Mintel, William

357 40, 357 43, 357 35, 357 54, 357 45, H01L 2348

Patent

active

049491628

ABSTRACT:
A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).

REFERENCES:
patent: 3667008 (1979-05-01), Katnick
patent: 4663831 (1987-05-01), Birritella et al.
patent: 4673969 (1987-06-01), Ariizumi et al.
patent: 4710794 (1987-12-01), Koshino et al.
patent: 4725874 (1988-02-01), Ooga et al.
patent: 4748489 (1988-05-01), Komatsu

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