Architecture for memory multiplexing

Details Architecture for memory multiplexing Architecture for memory multiplexing

1987-08-17

1989-06-06

Fears, Terrell W.

Excavating

36523002, 365241, 36518907, G11C 1140, G11C 1300

Patent

active

048377430

ABSTRACT:
A solid state memory system is arranged in a plurality of blocks of memory cells, the memory cells in each block arranged in columns and rows. When the memory system is addressed for a memory reference, block selection circuitry selects one block of the plurality of blocks, excluding all of the other blocks. Each block has a set of sense amplifiers, corresponding in number to the number of bits in the output word. Each sense amplifier is connected to an isolation switch. The outputs from the sense amplifiers connected to the non-selected blocks are thereby isolated from the sense amplifier outputs from the selected block to minimize loading of the sense amplifier outputs from the selected block. The memory cells in each block are interconnected by metal row conductors and by metal column conductors.

REFERENCES:
patent: 3402398 (1968-09-01), Koerner et al.

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