Semiconductor memory device with an improved multi-bit test mode

Details Semiconductor memory device with an improved multi-bit test mode Semiconductor memory device with an improved multi-bit test mode

1988-04-06

1990-02-06

Heinz, A. J.

Static information storage and retrieval

Read/write circuit

Testing

36518908, 36518904, 36523003, 371 212, G11C 700, G11C 800

Patent

active

048993131

ABSTRACT:
A memory device provides a test mode which simultaneously carries out the function test of plural bit memory cells. In this memory device, trilevel decision is carried out based on the AND operation on the memory cell information of the selected plural bits in the single device level while bilevel decision is carried out in the board level on the basis of the OR operation on the AND result of the information of the selected plural bit memory cells and the AND result of the inverted information of the same.

REFERENCES:
patent: 4543647 (1985-09-01), Yoshida
patent: 4654849 (1987-03-01), White et al.
patent: 4692901 (1987-09-01), Kumanoya et al.
patent: 4771407 (1988-09-01), Takema et al.
patent: 4811299 (1989-03-01), Miyazawa et al.
IEEE Int'l. Sol. St. Cir. Conf.: "A 90 ns 1 Mb DRAM with Multi-Bit Test Mode", by M. Kumanoya et al., 2/15/85, pp. 240-241.
IEEE J. of Sol. St. Cir.: "A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode", by M. Kumanoya et al., vol. Sc. 20, No. 5, Oct. 1985, pp. 909-913.
IEEE Int'l. Sol. St. Cir. Conf.: "A 60 ns DRAM in a 300 mi DIP", by T. Sumi et al., 2/27/87, pp. 282-283.
IEEE Int'l. Sol. St. Cir. Conf.: "A 70 ns 4 Mb DRAM in a 300 mil DIP Using 4-Layer Poly", by H. Mochizuki et al., 2/27/85, pp. 284-285.
Nikkei Electronics, 1987, 4.6, No. 418, pp. 149-163, includes English translation, Ishihara et al.

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