Methods and devices for accelerating failure of marginally defec

Details Methods and devices for accelerating failure of marginally defec Methods and devices for accelerating failure of marginally defec

1993-04-29

1994-03-22

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365149, G11C 700

Patent

active

052970876

ABSTRACT:
A semiconductor memory device includes a plurality of row lines, a plurality of column lines, and a common storage cell plate. The memory device also includes a cell plate generator which produces a reference voltage. The reference voltage is connected to the common storage cell plate. A row decoder connects a row line voltage to selected individual row lines. A stress mode detection circuit receives a row line stress voltage and generates a stress mode signal in response. The row decoder is responsive to the stress mode signal to simultaneously bias all of the row lines to the row line stress voltage. At least one equilibrate circuit is also connected to receive the stress mode signal and is responsive to the stress mode signal to bias the column lines to the reference voltage. The memory device is furthermore responsive to the stress mode signal to ground the reference voltage. The circuits described create a voltage stress differential between the column lines, the row lines, and the common storage cell plate. This voltage stress differential is greater than any voltage differential occurring between the row lines, the column lines, and the storage cell plate during normal memory access operations. The voltage stress differential is maintained for a relatively long period to induce failure of marginally defective dielectric layers within the semiconductor memory device.

REFERENCES:
patent: 4751679 (1988-06-01), Dehganpour
patent: 5155701 (1992-10-01), Komori et al.
patent: 5243569 (1993-09-01), Atsumi
patent: 5255229 (1993-10-01), Tanaka et al.

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