Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S163000

Reexamination Certificate

active

08085576

ABSTRACT:
A semiconductor memory device comprises: a memory cell array having memory cells disposed at a crossing-point of a plurality of first lines and a plurality of second lines and a control circuit configured to apply a first voltage to selected one or more of the first lines, and to apply a second voltage having a value smaller than the first voltage to selected one of the second lines, such that a certain potential difference is applied to selected one or more of the memory cells. The control circuit adjusts the second voltage based on a position of the selected one or more of the memory cells within the memory cell array and a number of the selected one or more of the memory cells on which an operation is simultaneously executed, during application of the potential difference to the selected one or more of the memory cells.

REFERENCES:
patent: 6141241 (2000-10-01), Ovshinsky et al.
patent: 7433222 (2008-10-01), Hosoi et al.
patent: 7542370 (2009-06-01), Yan et al.
patent: 7633788 (2009-12-01), Choi et al.
patent: 7920408 (2011-04-01), Azuma et al.
patent: 2010/0027317 (2010-02-01), Maejima
U.S. Appl. No. 12/884,965, filed Sep. 17, 2010, Hosono et al.
U.S. Appl. No. 12/556,272, filed Sep. 9, 2009, Koji Hosono et al.

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