Per-bit de-skew mechanism for a memory interface controller

Details Per-bit de-skew mechanism for a memory interface controller Per-bit de-skew mechanism for a memory interface controller

2009-05-08

2011-12-20

Hidalgo, Fernando (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S154000, C365S156000, C365S189011, C365S189140, C365S189050, C365S189080, C365S193000, C365S230060, C365S233100, C365S233130, C365S233170, C711S105000, C711S106000, C711S104000, C711SE12001

Reexamination Certificate

active

08081527

ABSTRACT:
A memory controller may implement variable delay elements, on a per-bit basis, in both the read and write paths. The memory controller may include multiple adjustable delay circuits associated with data lines and a strobe line, each of the adjustable delay circuits inserting an adjustable amount of delay into a signal destined to or received from one of the data lines or the strobe line. The memory controller may additionally include control logic to determine the delay amount for each of the adjustable delay circuits, the delay amount being determined to reduce static skew between each of the data lines and the strobe line.

REFERENCES:
patent: 2009/0109770 (2009-04-01), Sugishita
patent: 2009/0244997 (2009-10-01), Searles et al.
patent: 2010/0157700 (2010-06-01), Kong et al.

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