Structure for dynamically adjusting pipelined data paths for...

Details Structure for dynamically adjusting pipelined data paths for... Structure for dynamically adjusting pipelined data paths for...

2007-10-09

2011-12-27

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C710S260000, C718S107000, C718S108000

Reexamination Certificate

active

08086832

ABSTRACT:
A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.

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