Semiconductor memory device and read wait time adjustment...

Details Semiconductor memory device and read wait time adjustment... Semiconductor memory device and read wait time adjustment...

2010-01-14

2011-11-08

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S230060

Reexamination Certificate

active

08054700

ABSTRACT:
A semiconductor memory device operates in synchronization with a system clock, without using a synchronous circuit such as a DLL or a PLL. The semiconductor memory device includes a synchronous circuit for generating output signals phase aligned with the system clock, a synchronous circuit selection circuit that performs switching between a synchronous circuit selection mode and a synchronous circuit non-selection mode, and a reference edge specifying register that specifies an edge of an internal clock which serves as a reference for outputting read data in the synchronous circuit non-selection mode. In the synchronous circuit selection mode, the read data is output by adjusting a phase deviation of the internal clock with respect to the system clock, using the synchronous circuit. In the synchronous circuit non-selection mode, the read data is output in synchronization with the internal clock, without using the synchronous circuit. For a delay of the internal clock with respect to the system clock, the edge of the internal clock used as the reference is adjusted by the reference edge specifying register. Then, even if the synchronous circuit is not used, a large timing deviation does not thereby occur.

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JEDEC Standard DDR3 SDRAM Specification, JESD79-3B, Apr. 2008, JEDEC Solid State Technology Association (JEDEC Solid State Technology Association) pp. 37-41.

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