Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Capacitors

Reexamination Certificate

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Reexamination Certificate

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08036021

ABSTRACT:
A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.

REFERENCES:
patent: 6984857 (2006-01-01), Udayakumar et al.
patent: 2003/0169616 (2003-09-01), Noro
patent: 2006/0047034 (2006-03-01), Sakurai et al.
patent: 11-026719 (1999-01-01), None
patent: 2000-049304 (2000-02-01), None
patent: 2002-133892 (2002-05-01), None
patent: 2004-221473 (2004-08-01), None
Yanagiya et al., “65nm CMOS Technology (CMOS5) with High Density Embedded Memories for Broadband Microprocessor Applications”IEEE, 2002; p. 57-60.
Office Action received for corresponding Japanese Patent Application 2006-348870 mailed Mar. 1, 2011.
Office Action received for corresponding Japanese Patent Application 2006-348870 mailed on Jul. 19, 2011.

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