Semiconductor device with large blocking voltage

Active solid-state devices (e.g. – transistors – solid-state diode – Specified wide band gap semiconductor material other than... – Diamond or silicon carbide

Reexamination Certificate

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C257S049000, C257S256000, C257S262000, C257S267000, C257S272000, C257S273000, C257SE27016, C257SE27017, C257SE27024, C257SE27068, C257SE27069, C257SE27073, C257SE29059, C257SE29194, C257SE29195

Reexamination Certificate

active

08049223

ABSTRACT:
A junction FET having a large gate noise margin is provided. The junction FET comprises an n−layer forming a drift region of the junction FET formed over a main surface of an n+substrate made of silicon carbide, a p+layer forming a gate region formed in contact with the n−layer forming the drift region and a gate electrode provided in an upper layer of the n+substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+substrate and electrically connecting the p+layer forming the gate region and the gate electrode.

REFERENCES:
patent: 6107649 (2000-08-01), Zhao
patent: 2002/0113274 (2002-08-01), Iwagami et al.
patent: 2004/0135178 (2004-07-01), Onose et al.
patent: 2004-134547 (2003-04-01), None
S. Harada et al., “1.8 mΩcm2, 10 A Power MOSFET in 4H-SiC,” Proceedings of International Electron Device Meeting 2006.

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