On-die termination control circuit of semiconductor memory...

Details On-die termination control circuit of semiconductor memory... On-die termination control circuit of semiconductor memory...

2008-05-28

2011-10-25

Ismail, Shawki (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C327S108000, C333S017300, C333S032000

Reexamination Certificate

active

08044679

ABSTRACT:
On-die termination control circuit of semiconductor memory device includes a counter configured to count an external clock to output a first code, and to count an internal clock to output a second code, a transfer controller configured to determine whether to transfer the first code and the second code in response to a first termination command and a normal termination controller configured to compare the first code and the second code with each other to determine enabling/disabling timings of a termination operation in response to a second termination command.

REFERENCES:
patent: 7365564 (2008-04-01), Kim
patent: 2007/0126468 (2007-06-01), Kim
patent: 2008/0054936 (2008-03-01), Fujisawa
patent: 2009/0016124 (2009-01-01), Kim
patent: 2009/0115450 (2009-05-01), Kim et al.
patent: 2010/0001762 (2010-01-01), Kim
patent: 2010/0207680 (2010-08-01), Kuwahara et al.
patent: 2010/0208534 (2010-08-01), Fujisawa
patent: 1020070036635 (2007-04-01), None
patent: 1020080114086 (2008-12-01), None

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