Insulated gate field-effect transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S213000, C257S368000

Reexamination Certificate

active

08030708

ABSTRACT:
The invention aims at precisely making an effective junction depth sufficiently small with respect to a substrate surface having a steep PN junction stable in its configuration and having a channel formed therein in relation to an extension portion. Gate electrodes are formed on a P-type well and an N-type well through respective gate insulating films. Two extension portions are formed from two first epitaxial growth layers which contact regions, of the P-type well and the N-type well, where channels are to be formed, respectively, and which are at a distance from each other. Two second epitaxial growth layers are formed on the first epitaxial growth layers in positions which are further at a distance from facing ends of the two extension portions in a direction of being separate from each other. Thus, two source/drain regions are formed on a PMOS side and on an NMOS side each. In the case of this structure, there is adopted no ion implantation for introducing impurities into a deep portion. Hence, the impurities in the extension portions do not thermally diffuse into the substrate side through the activation anneal.

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Shigeru Nishimatsu, et al., “Groove Gate MOSFET, 8th Conference On Solid State Devices,” Japanese Journal of Applied Physics, 1976, Supplement 16-1, vol. 16, pp. 179 to 183.
Takashi Uchino, et al. “A Raised Source/Drain Technology Using In-situ P-doped SiGe and B-doped Si for 0.1 μm CMOS ULSIs,” IEDM 1997, pp. 479 to 482.
Japanese Office Action dated May 18, 2011 for Japanese Application No. 2005-001608.

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