Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE27112, C365S230060

Reexamination Certificate

active

08035147

ABSTRACT:
A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.

REFERENCES:
patent: 5148393 (1992-09-01), Furuyama
patent: 2005/0253197 (2005-11-01), Tokushige
patent: 2005/0276094 (2005-12-01), Yamaoka et al.
patent: 2006/0158924 (2006-07-01), Sekiguchi et al.
patent: 2007/0210418 (2007-09-01), Nakajima
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patent: 2005-251776 (2005-09-01), None
M. Yamaoka et al., “Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology,” 2004 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2004, pp. 288-291.
R. Tsuchiya et al., “Silicon on Thin BOX: A new Paradigm of the CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control,” IEDM Dig. Tech. Papers, Dec. 2004, pp. 631-634.
Translation of Office Action from Japanese Patent Application No. 2005-373757.

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