Single poly EEPROM without separate control gate nor erase...

Details Single poly EEPROM without separate control gate nor erase... Single poly EEPROM without separate control gate nor erase...

2007-03-12

2011-11-29

Gebremariam, Samuel (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000

Reexamination Certificate

active

08067795

ABSTRACT:
A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein the source-to-floating gate capacitance is substantially greater than the drain-to-floating gate capacitance. The source-to-floating gate capacitance is, for example, at least about three times greater than the drain-to-floating gate capacitance to enable the memory device to be electrically programmed or erased by applying a potential between a source electrode and a drain electrode without using a control gate. A current path between the source and drain electrodes generally defines current carrying portions of the source and drain regions, and a non-current carrying portion of the source region residing outside the current carrying portion, wherein substantially more of the floating gate overlies the non-current carrying portion than the current carrying portions.

REFERENCES:
patent: 5751635 (1998-05-01), Wong et al.
patent: 6031771 (2000-02-01), Yiu et al.
patent: 6044018 (2000-03-01), Sung et al.
patent: 7489550 (2009-02-01), Tanaka

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