Integration of planar and tri-gate devices on the same...

Details Integration of planar and tri-gate devices on the same... Integration of planar and tri-gate devices on the same...

2009-01-29

2011-11-15

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE21442, C257SE21661, C257SE27098, C365S188000

Reexamination Certificate

active

08058690

ABSTRACT:
An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed.

REFERENCES:
patent: 5804848 (1998-09-01), Mukai
patent: 5844278 (1998-12-01), Mizuno et al.
patent: 5899710 (1999-05-01), Mukai
patent: 6018176 (2000-01-01), Lim
patent: 6066869 (2000-05-01), Noble et al.
patent: 6271542 (2001-08-01), Emma et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6459123 (2002-10-01), Enders et al.
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6583469 (2003-06-01), Fried et al.
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6630388 (2003-10-01), Sekigawa et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6657259 (2003-12-01), Fried et al.
patent: 6689650 (2004-02-01), Gambino et al.
patent: 6770516 (2004-08-01), Wu et al.
patent: 6787402 (2004-09-01), Yu
patent: 6794718 (2004-09-01), Nowak et al.
patent: 6798000 (2004-09-01), Luyken et al.
patent: 6800910 (2004-10-01), Lin et al.
patent: 6803631 (2004-10-01), Dakshina-Murthy et al.
patent: 6812075 (2004-11-01), Fried et al.
patent: 6815277 (2004-11-01), Fried et al.
patent: 6821834 (2004-11-01), Ando
patent: 6833588 (2004-12-01), Yu et al.
patent: 6835614 (2004-12-01), Hanafi et al.
patent: 6849884 (2005-02-01), Clark et al.
patent: 6867460 (2005-03-01), Anderson et al.
patent: 6869868 (2005-03-01), Chiu et al.
patent: 6885055 (2005-04-01), Lee
patent: 6897527 (2005-05-01), Dakshina-Murthy et al.
patent: 6924560 (2005-08-01), Wang et al.
patent: 6949768 (2005-09-01), Anderson et al.
patent: 7414877 (2008-08-01), Burnett et al.
patent: 7512017 (2009-03-01), Chang
patent: 2004/0266076 (2004-12-01), Doris et al.
patent: 2006/0125021 (2006-06-01), Bhattacharyya
patent: 2006/0281236 (2006-12-01), Datta et al.
patent: 2007/0045748 (2007-03-01), Booth, Jr. et al.
patent: 2007/0069293 (2007-03-01), Kavalieros et al.
patent: 2007/0108528 (2007-05-01), Anderson et al.
patent: 2007/0264762 (2007-11-01), Yeo et al.
patent: 2008/0128759 (2008-06-01), Chang
patent: WO 2004/084292 (2004-09-01), None
C.H. Lee et al., “Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for Sub 60nm Technology and Beyond,” IEEE, 2004, pp. 130-131.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” IEEE, 2001, 4 pages.
Jong-Tae Park et al., “Pi-Gate SOI MOSFET,” IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, pp. 405-406.
Zheng Guo et al., “FinFET-Based SRAM Design,” Proceedings of the 2005 IEEE International Symposium on Low Power Electronics and Design, San Diego, CA, Aug. 8, 2005.
PCT International Search Report for Application No. PCT/US2006/047149, Mailed May 4, 2007.
International Preliminary Report on Patentability and PCT Written Opinion PCT/US2006/047149, Mailed Jun. 24, 2008.
Office Action mailed on Jun. 16, 2008, U.S. Appl. No. 11/313,351, filed Dec. 21, 2005, Peter L.D. Chang, pp. 1-5.
Office Action mailed on Jul. 31, 2008, U.S. Appl. No. 11/313,351, filed Dec. 21, 2005, Peter L.D. Chang, pp. 1-9.
U.S. Notice of Allowance mailed Nov. 14, 2008, U.S. Appl. No. 11/313,351, filed Dec. 21, 2005 (8 pages).

Affiliated with

Also associated with

Rating

Integration of planar and tri-gate devices on the same... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integration of planar and tri-gate devices on the same..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integration of planar and tri-gate devices on the same... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4283046