Semiconductor device and method of manufacturing...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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Details

C438S150000, C438S157000, C438S164000, C257SE21199, C257SE21411, C257SE21622

Reexamination Certificate

active

08053292

ABSTRACT:
The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

REFERENCES:
patent: 7015082 (2006-03-01), Doris et al.
patent: 7473967 (2009-01-01), Sorada et al.
patent: 2006/0057787 (2006-03-01), Doris et al.
patent: 2006/0175667 (2006-08-01), Tsuchiaki
patent: 2006/0284255 (2006-12-01), Shin et al.
patent: 2009/0101982 (2009-04-01), Nagatomo
Thompson et al., “In Search of ‘Forever’ Continued Transistor Scaling One New Material at a Time,” IEEE Transactions on Semiconductor Manufacturing (2005), 18:26-36.
Thompson et al., “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions on Electron Devices (2004), 51:1790-97.

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