Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2008-08-27
2011-11-22
Kim, Hong (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S136000, C711S144000, C711S145000
Reexamination Certificate
active
08065496
ABSTRACT:
To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage data0stored in the leftmost position indicates an ID of an entry with the oldest last use time (that is, LRU entry), for example as shown in FIG.1(1). An LRU control apparatus according to a first embodiment of the present invention refers to the LRU information, and selects an entry corresponding to the storage data0(for example, entry1) from the LRU information as a candidate for the LRU control, based on the storage data0as the ID of the entry with the oldest last use time.
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Japanese Office Action issued on Apr. 7, 2009 in corresponding Japanese Patent Application 2008-501578.
International Search Report mailed Jun. 27, 2006 in connection with International Application No. PCT/JP2006/303620.
Kojima Hiroyuki
Okawa Tomoyuki
Ukai Masaki
Fujitsu Limited
Fujitsu Patent Center
Kim Hong
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