Memory controllers, memory systems, solid state drives and...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S006000, C710S021000, C710S024000, C710S028000, C710S040000, C710S054000

Reexamination Certificate

active

08055816

ABSTRACT:
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

REFERENCES:
patent: 4654791 (1987-03-01), Ushiro
patent: 4797812 (1989-01-01), Kihara
patent: 4811306 (1989-03-01), Boning et al.
patent: 5182800 (1993-01-01), Farrell et al.
patent: 5517670 (1996-05-01), Allen et al.
patent: 5526484 (1996-06-01), Casper et al.
patent: 5539918 (1996-07-01), Allen et al.
patent: 5564055 (1996-10-01), Asnaashari et al.
patent: 5640596 (1997-06-01), Takamoto et al.
patent: 5717952 (1998-02-01), Christiansen et al.
patent: 5742792 (1998-04-01), Yanai et al.
patent: 5901327 (1999-05-01), Ofek
patent: 5928370 (1999-07-01), Asnaashari
patent: 5978890 (1999-11-01), Ozawa et al.
patent: 6012104 (2000-01-01), Van Nguyen et al.
patent: 6076137 (2000-06-01), Asnaashari
patent: 6134151 (2000-10-01), Estakhri et al.
patent: 6173377 (2001-01-01), Yanai et al.
patent: 6185521 (2001-02-01), Vishlitzky
patent: 6192444 (2001-02-01), White et al.
patent: 6233660 (2001-05-01), Vishlitzky
patent: 6321292 (2001-11-01), Ozawa et al.
patent: 6327639 (2001-12-01), Asnaashari
patent: 6470432 (2002-10-01), Ozawa et al.
patent: 6915378 (2005-07-01), Roberti
patent: 7102671 (2006-09-01), Asnaashari
patent: 7296110 (2007-11-01), Chung et al.
patent: 7373465 (2008-05-01), Hiramatsu et al.
patent: 2002/0078292 (2002-06-01), Chilton
patent: 2002/0199072 (2002-12-01), Fanning
patent: 2005/0021921 (2005-01-01), Blackmon et al.
patent: 2005/0036453 (2005-02-01), Lin et al.
patent: 2006/0271697 (2006-11-01), Kruse et al.
patent: 2007/0283109 (2007-12-01), Kelly
patent: 2008/0016294 (2008-01-01), Hillier, III et al.
patent: 2008/0107275 (2008-05-01), Asnaashari
patent: 2008/0140919 (2008-06-01), Torabi et al.
patent: 2008/0177909 (2008-07-01), Sapp et al.
patent: 2008/0235443 (2008-09-01), Chow et al.
Intel Dual-Channel DDR Memory Architecture, Sep. 2003, Infinion Technologies & Kingston Technology, [online, accessed on Jul. 15, 2011], URL: http://www.kingston.com
ewtech/mkf—520ddrwhitepaper.pdf.
International Search Report and Written Opinion for related PCT Application PCT/US2010/000732, mailed Nov. 3, 2010 (9 pgs.).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Memory controllers, memory systems, solid state drives and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory controllers, memory systems, solid state drives and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controllers, memory systems, solid state drives and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4272743

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.