SRAM bit cell with self-aligned bidirectional local...

Details SRAM bit cell with self-aligned bidirectional local... SRAM bit cell with self-aligned bidirectional local...

2009-06-01

2011-12-13

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C439S299000, C439S675000, C257SE21641

Reexamination Certificate

active

08076236

ABSTRACT:
Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

REFERENCES:
patent: 6180530 (2001-01-01), Liaw et al.
patent: 2007/0034968 (2007-02-01), Nishida et al.
Schultz, Richard T.,Selective Local Interconnect to Gate in a Self Aligned Local Interconnect Process, U.S. Appl. No. 12/475,796, filed Jun. 1, 2009.

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