Using register rename maps to facilitate precise exception...

Details Using register rename maps to facilitate precise exception... Using register rename maps to facilitate precise exception...

2008-12-12

2011-12-13

Faherty, Corey S (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S218000, C712S228000

Reexamination Certificate

active

08078854

ABSTRACT:
One embodiment of the present invention provides a system that facilitates precise exception semantics. The system includes a processor that uses register rename maps to support out-of-order execution, where the register rename maps track mappings between native architectural registers and physical registers for a program executing on the processor. These register rename maps include: 1) a working rename map that maps architectural registers associated with a decoded instruction to corresponding physical registers; 2) a retire rename map that tracks and preserves a set of physical registers that are associated with retired instructions; and 3) a checkpoint rename map that stores a mapping between a set of architectural registers and a set of physical registers for a preceding checkpoint in the program. When the program signals an exception, the processor uses the checkpoint rename map to roll back program execution to the preceding checkpoint.

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