Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2010-04-07
2011-11-29
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S742000
Reexamination Certificate
active
08069380
ABSTRACT:
A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.
REFERENCES:
patent: 4333142 (1982-06-01), Chesley
patent: 5434825 (1995-07-01), Harari
patent: 5525971 (1996-06-01), Flynn
patent: 5566303 (1996-10-01), Tashiro et al.
patent: 5566344 (1996-10-01), Hall et al.
patent: 5598573 (1997-01-01), Hall et al.
patent: 5606710 (1997-02-01), Hall et al.
patent: 5613144 (1997-03-01), Hall et al.
patent: 5623686 (1997-04-01), Hall et al.
patent: 5896398 (1999-04-01), Sekine
patent: 6009539 (1999-12-01), Ranson
patent: 6151692 (2000-11-01), Smitlener et al.
patent: 6198663 (2001-03-01), Takizawa
patent: 6311273 (2001-10-01), Helbig, Sr. et al.
patent: 6426893 (2002-07-01), Conley et al.
patent: 6551844 (2003-04-01), Eldridge et al.
patent: 6636825 (2003-10-01), Malladi et al.
patent: 6797538 (2004-09-01), Wallace
patent: 6832348 (2004-12-01), Kawabe et al.
patent: 7631245 (2009-12-01), Lasser
patent: 7752380 (2010-07-01), Avraham et al.
patent: 2002/0174382 (2002-11-01), Ledford et al.
patent: 2004/0083334 (2004-04-01), Chang et al.
patent: 2005/0149780 (2005-07-01), Avraham
patent: 2005/0156165 (2005-07-01), Eldridge et al.
patent: 1452070 (2003-10-01), None
patent: 1416380 (2004-06-01), None
patent: 2000-305799 (2000-11-01), None
patent: 10-2004-0038709 (2004-05-01), None
patent: 2004010437 (2004-01-01), None
Seki, K.; Kume, H.; Ohji, Y.; Kobayashi, T.; Hiraiwa, A.; Nishida, T.; Wada, T.; Komori, K.; Izawa, K.; Nishimoto, T.; Kubota, Y.; Shoji, K.; , “An 80-ns. 1-Mb flash memory with on-chip erase/erase-verify controller,” Solid-State Circuits, IEEE Journal of , vol. 25, No. 5, pp. 1147-1152, Oct. 1990 doi: 10.1109/4.62136.
Campardo, Giovanni et al. “An Overview of Flash Architectural Developments,” Proceedings of the IEEE, vol. 91, No. 4, Apr. 2003, pp. 523-536.
International Search Report and Written Opinion for International Application No. PCT/IL06/01247 dated Oct. 27, 2008, 7 pages.
Office Action dated Jan. 20, 2011 issued in Chinese Application No. 200680049485.7 with English translation, 12 pages.
Notice of Grounds for Rejection dated Sep. 30, 2009 issued in Korean Application No. 10-2008-7013212 with English translation, 15 pages.
English translation of Notice of Grounds for Rejection dated Mar. 31, 2010 issued in Korean Application No. 10-2008-7013212, 5 pages.
Notice of Allowance and Fee(s) Due dated Jan. 8, 2010 issued in U.S. Appl. No. 11/397,578, 7 pages.
Restriction Requirement dated Aug. 18, 2009 issued in U.S. Appl. No. 11/397,578, 6 pages.
Non-Final Office Action dated Dec. 31, 2008 issued in U.S. Appl. No. 11/397,578, 13 pages.
Notification of Reasons of Rejection dated Jun. 10, 2011 issued in Japanese Patent Application No. 2008-537314 with English translation, 7 pages.
Lasser Menahem
Meir Avraham
Murin Mark
Britt Cynthia
Sandisk IL Ltd.
Toler Law Group
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