Transistor level routing

Details Transistor level routing Transistor level routing

2009-06-09

2011-12-13

Lee, Eugene (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S508000, C257S204000, C257SE23141, C257SE23142, C257SE23143, C257SE23144, C257SE23145

Reexamination Certificate

active

08076730

ABSTRACT:
System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first poly-silicon layer. The semiconductor device further includes a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second poly-silicon layer. An electrical connection connects the first semiconductor device with the second semiconductor device and overlies the first active area, the second active area and a portion of the substrate between the first active area and the second active area. The electrical connection includes a high-k dielectric layer and a metal layer but not a poly-silicon layer and the metal layer is arranged directly over the high-k dielectric layer.

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