Programmable arithmetic logic unit cluster

Details Programmable arithmetic logic unit cluster Programmable arithmetic logic unit cluster

2010-10-12

2011-11-01

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

C712S016000, C716S116000

Reexamination Certificate

active

08051277

ABSTRACT:
A Programmable Arithmetic Logic Unit Cluster is claimed. The plurality of Programmable Logic Blocks (50) in the cluster are in a physically linear sequence; but, will process data in parallel when the data pathways permit. A physically linear and operationally parallel design is possible mainly due to an Internal Register Bus (30). A small subset of data from the Internal Register Bus (30) is modified by each Arithmetic Logic Unit (53). The greater chunk of information of the Internal Register Bus (30) passes, without changes made to the data, through a plurality of two-to-one-multiplexers (54) as data inputs, bypassing the Data Selection (52) and Arithmetic Logic Unit's (53) circuitry. Only the data specified as the Accumulator (41) and Carry History (31) are modified by the blocks (50). The Accumulator (41) and the Carry Output Line (44) are distributed back onto the Internal Register Bus (30) for subsequent blocks or for the Output Register File (79) by said two-to-one-multiplexers (54).

REFERENCES:
patent: 6286101 (2001-09-01), Suzuki
patent: 6574761 (2003-06-01), Abramovici et al.
patent: 2002/0083308 (2002-06-01), De Oliveira Kastrup Pereira et al.
patent: 2003/0005402 (2003-01-01), Bal
patent: 2004/0178818 (2004-09-01), Crotty et al.

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