Memory with five-transistor bit cells and associated control...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S104000, C365S156000

Reexamination Certificate

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08072796

ABSTRACT:
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.

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International Search Report and Written Opinion, issued in International Patent Application No. PCT/EP2007/000655, mailed Apr. 5, 2007, 11 pages.
International Preliminary Report on Patentability, issued in International Patent Application No. PCT/EP2007/000655, mailed Sep. 4, 2008, 8 pages.

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