Structure for dual-mode memory chip for high capacity memory...

Details Structure for dual-mode memory chip for high capacity memory... Structure for dual-mode memory chip for high capacity memory...

Filed on

2008-03-21

Date issued

2011-10-11

Examiner

Lo, Kenneth M (Department: 2189)

Patent Class

Electrical computers and digital processing systems: memory

SubClass

Storage accessing and control

SubSubClass

Control technique

Other Related Categories

C711S167000, C711S165000, C711SE12006

Type

Reexamination Certificate

Status

active

Patent number

08037258

Description

ABSTRACT:
A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.

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