SRAM and testing method of SRAM

Details SRAM and testing method of SRAM SRAM and testing method of SRAM

2010-02-03

2011-12-27

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S203000

Reexamination Certificate

active

08085610

ABSTRACT:
An SRAM includes a memory cell; and a control circuit configured to change a signal level of a signal which is used in an ordinary mode for access to the memory cell in a test mode to apply a disturbance to the memory cell. The control circuit can change the signal level to set a level of the disturbance optionally.

REFERENCES:
patent: 6778451 (2004-08-01), Takahashi et al.
patent: 7672181 (2010-03-01), Mori et al.
patent: 2003/0072187 (2003-04-01), Takahashi et al.
patent: 2008/0137456 (2008-06-01), Shimosaka
patent: 2009/0040851 (2009-02-01), Mori et al.
patent: 7-182895 (1995-07-01), None
Meixer et al. “Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique”, International Test Conference, Paper BP, IEEE, 0-7803-4209-7/1997.

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