Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2008-06-27
2011-12-06
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S223000, C365S233110, C365S193000
Reexamination Certificate
active
08072824
ABSTRACT:
An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.
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Graham Kretelia
Greenblum & Bernstein P.L.C.
Panasonic Corporation
Zarabian Amir
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