Operation guarantee system

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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Details

C365S223000, C365S233110, C365S193000

Reexamination Certificate

active

08072824

ABSTRACT:
An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.

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patent: 8-110872 (1996-04-01), None
patent: 8-137783 (1996-05-01), None
patent: 2001-160000 (2001-06-01), None
patent: 2001-290697 (2001-10-01), None
patent: 2002-366421 (2002-12-01), None
patent: 2005-141725 (2005-06-01), None
patent: 2005-530297 (2005-10-01), None
patent: 2006-107352 (2006-04-01), None
patent: 2006-189916 (2006-07-01), None
patent: 2006-338130 (2006-12-01), None
English language Abstract of JP 8-110872, Apr. 30, 1996.
English language Abstract of JP 8-137783, May 31, 1996.
English language Abstract of JP 2006-338130, Dec. 14, 2006.
English language Abstract of JP 2001-160000, Jun. 12, 2001.

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