Semiconductor device and method of forming WLP with...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C438S107000, C438S118000, C438S124000, C438S127000, C438S455000, C257SE21499, C257SE21500, C257SE21502, C257SE21503, C257SE21513

Reexamination Certificate

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08080445

ABSTRACT:
A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.

REFERENCES:
patent: 2005/0067714 (2005-03-01), Rumer et al.
patent: 2006/0289984 (2006-12-01), Fontana et al.
patent: 2007/0205495 (2007-09-01), Fernandez et al.
patent: 2009/0134515 (2009-05-01), Hu
patent: 2009/0166825 (2009-07-01), Camacho et al.
patent: 2009/0184784 (2009-07-01), Chun et al.
patent: 2010/0065948 (2010-03-01), Bae et al.
patent: 2010/0072618 (2010-03-01), Camacho et al.
Kripesh, V., “EMC-3d Seminar, Silicon Substrate Technology for SiP Modules”, pp. 1-61, Institute of Microelectronics, Singapore, Jan. 23, 2007.

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